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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9807/ad9805 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 complete 12-bit /10-bit 6 msps ccd/cis signal processors functional block diagram pga pga pga green red blue mux adc ref gain registers input offset config regs odd even 8-10 12-10 12-10 mpu port csb rd wr a2 a1 a0 vref pixel offset pixel gain cdsclk1 cdsclk2 adcclk vinr ving vinb dout AD9807/ad9805 pga pga gain registers mux ref input offset config regs even odd mpu port x cds cds cds production description the AD9807 and ad9805 are complete ccd/cis imaging decoders and signal processors on a single monolithic integrated circuit. the input of the AD9807/ad9805 allows direct ac coupling of the charge-co upled device (ccd) or co ntact image sensor (cis) output(s). the AD9807/ad9805 includes all the circuitry to perform three-channel correlated double sampling (cds) and programmable gain adjustment of the ccd output; a 12-bit or 10-bit analog-to-digital converter (adc) quantizes the analog signal. after digitization, the on-board digital signal proces sor (dsp) circuitry allows pixel rate offset and gain correc- tion. the dsp also corrects odd/even ccd register imbalance errors. a parallel control bus provides a simple interface to 8-bit microc ontrolle rs. the AD9807/ad9805 comes in a space saving 64- pin plastic quad flatpack (pqfp) and is specified over the commercial (0 c to +70 c) temperature range. by disabling the cds, the AD9807/ad9805 are also suitable for non-ccd applications, or applications that do not require cds, such as cis signal processing. product highlights the AD9807/ad9805 offers a complete, single chip ccd imaging front end in a 64-pin plastic quad flatpack (pqfp). on-chip pga the AD9807/ad9805 includes a 3-channel analog programmable gain amplifier; it is programmable from 1 to 4 in 16 increments. on-chip cds an integrated 3-channel correlated double sampler allows easy ac coupling directly from the ccd sensor outputs. additionally, the cds reduces low frequency noise and reset feedthrough. on-chip voltage reference the AD9807/ad9805 includes a 2 v bandgap reference that allows the input range of the device to be configured for input spans up to 4 v. 6 msps a/d converter a highly linear 12-bit or 10-bit a/d converter sequentially digitizes the red, green and blue cds outputs ensuring no missing code performance. the user may also configure the AD9807/ad9805 for single channel operation. digital gain & offset correction pixel rate digital gain and offset correction blocks allow precise repeatable correction of imaging system error sources. digital i/o compatibility the AD9807/ad9805 offers +3.3 v/+5 v logic level compatibility. pin-compatible 12-bit and 10-bit versions the AD9807 is also offered in a pin-compatible 10-bit version, the ad9805, allowing upgrad e-ability and simplifying design issues across different scanner models. features pin compatible 12-bit and 10-bit versions 12-bit/10-bit 6 msps a/d converter integrated triple correlated double sampler 3-channel, 2 msps color mode 1 3 C 4 3 analog programmable gain amplifier pixel-rate digital gain adjustment pixel-rate digital offset adjustment internal voltage reference no missing codes guaranteed microprocessor-compatible control interface +3.3 v/+5 v digital i/o compatibility low power cmos: 500 mw 64-pin pqfp surface mount package
C2C rev. 0 parameter min typ max units resolution 12 bits conversion rate 3-channel mode with cds 6 msps 1-channel mode with cds 1 6 msps dc accuracy integral nonlinearity (inl) 2 1.5 lsb differential nonlinearity (dnl) 2 0.4 0.75 lsb no missing codes 12 bits guaranteed unipolar offset error (@ +25 c) 0.4 % fsr gain error (@ +25 c) 1.2 % fsr analog inputs full-scale input span 0.0625 4 v p-p input limits 3 av ss C 0.3 v av dd + 0.3 v input capacitance 10 pf input bias current 0.01 m a input referred noise 0.3 lsb rms psrr (av dd = +5 v 0.25 v) 0.06 % fsr internal voltage reference 1 v output tolerance (@+25 c) 15 mv 2 v output tolerance (@+25 c) 30 mv power supplies operating voltages av dd +4.75 +5.25 v dv dd +4.75 +5.25 v operating current av dd 73 86 ma dv dd 16.6 20 ma power consumption 450 530 mw temperature range operating 0 +70 c notes 1 blue and green channels. red channel conversion rate for 1-channel mode is 5 msps. 2 measured with 4 v p-p input range. 3 input signals exceeding these limits are subject to excessive overvoltage recovery times. specifications subject to change without notice. analog specifications digital specifications parameter symbol min typ max units logic inputs high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage (i oh = 50 m a) v oh 4.5 4.9 v high level output voltage (i oh = 0.5 ma) v oh 2.4 v low level output voltage (i ol = 50 m a) v ol 0.1 v low level output voltage (i ol = C0.6 ma) v ol 0.4 v output capacitance c out 5pf specifications subject to change without notice. (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, f adcclk = 6 msps, f cdsclk1 = 2 msps, f cdsclk2 = 2 msps, c l = 20 pf, unless otherwise noted) (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, f adcclk = 6 msps, f cdsclk1 = 2 msps, f cdsclk2 = 2 msps, pga gain = 1 unless otherwise noted) AD9807Cspecifications C3C rev. 0 AD9807/ad9805 parameter min typ max units resolution 10 bits conversion rate 3-channel mode with cds 6 msps 1-channel mode with cds 1 6 msps dc accuracy integral nonlinearity (inl) 2 1.0 lsb differential nonlinearity (dnl) 2 0.5 lsb no missing codes 10 bits guaranteed unipolar offset error (@ +25 c) 0.6 % fsr gain error (@ +25 c) 1.2 % fsr analog inputs full-scale input span 0.0625 4 v p-p input limits 3 av ss C 0.3 v av dd + 0.3 v input capacitance 10 pf input bias current 0.01 m a input referred noise 0.1 lsb rms psrr (av dd = +5 v 0.25 v) 0.06 % fsr internal voltage reference 1 v output tolerance (@ +25 c) 15 mv 2 v output tolerance (@ +25 c) 30 mv power supplies operating voltages av dd +4.75 +5.25 v dv dd +4.75 +5.25 v operating current av dd 73 86 ma dv dd 16.6 20 ma power consumption 450 530 mw temperature range operating 0 +70 c notes 1 blue and green channels. red channel conversion rate for 1-channel mode is 5 msps. 2 measured with 4 v p-p input range. 3 input signals exceeding these limits are subject to excessive overvoltage recovery times. specifications subject to change without notice. analog specifications digital specifications parameter symbol min typ max units logic inputs high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 10 m a low level input current i il 10 m a input capacitance c in 10 pf logic outputs high level output voltage (i oh = 50 m a) v oh 4.5 4.9 v high level output voltage (i oh = 0.5 ma) v oh 2.4 v low level output voltage (i ol = 50 m a) v ol 0.1 v low level output voltage (i ol = C0.6 ma) v ol 0.4 v output capacitance c out 5pf specifications subject to change without notice. (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, f adcclk = 6 msps, f cdsclk1 = 2 msps, f cdsclk2 = 2 msps, c l = 20 pf, unless otherwise noted) (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, f adcclk = 6 msps, f cdsclk1 = 2 msps, f cdsclk2 = 2 msps, pga gain = 1 unless otherwise noted) ad9805Cspecifications AD9807/ad9805 C4C rev. 0 timing specifications parameter symbol min typ max units clock parameters 3-channel conversion rate t cra 500 ns 1-channel conversion rate t crb 166 ns cdsck1 pulse width t c1a 30 ns cdsck1 pulse width t c1b 30 ns cdsck2 pulse width t c2a 30 ns cdsck2 pulse width t c2b 30 ns cds clocks digital quiet time t q 20 ns cdsck2 falling to cdsck1 rising t c2c1a 80 ns cdsck2 falling to cdsck1 rising t c2c1b 40 ns cdsck1 falling to cdsck2 rising t c1c2a 20 ns cdsck1 falling to cdsck2 rising t c1c2b 20 ns adcclk rising to cdsck1 falling t c1ad 35 ns adcclk pulse width t aclk 50 ns adcclk period t cp 166 ns adcclk period (red single channel mode) t cp2 200 ns 3-channel settling time t stl1 60 ns 1-channel settling time (b and g only) t stl2 30 ns adcclk rising to control data setup t gos 15 ns adcclk rising to control data hold t goh 15 ns strtln rising, falling setup t s 15 ns strtln rising, falling hold t h 15 ns aperture delay t ad 10 ns register write/read address setup time t as 15 ns address hold time t ah 15 ns data setup time t ds 15 ns data hold time t dh 15 ns chip select setup time t css 15 ns chip select hold time t csh 15 ns write pulse width t pww 25 ns read pulse width t pwr 50 ns read to data valid t dd 40 ns data output output delay t od 15 ns 3-state to data valid t edv 15 ns output enable high to 3-state t hz 5ns latency 6 adcclk cycles (t min to t max with av dd = +5.0 v, dv dd = +5.0 v, unless otherwise noted) table i. output controls csb 00000011 rdb 001111xx wrb 010011xx oeb xx010101 dout xqxdxz qz mpu mpu adc legend: x = don't care x = unknown (not recommended) q = outputs d = inputs z = 3-state AD9807/ad9805 C5C rev. 0 pin configuration 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 55 54 53 52 51 50 49 59 58 57 56 pin 1 identifier top view (not to scale) gain<11> gain<10> gain<9> gain<8> gain<7> gain<6> gain<5> gain<4> gain<3> gain<2> gain<1> gain<0> dvss dvdd a2 a1 avdd avss capt capt capb capb vref cml vinr avss ving avss vinb avss avdd strtln a0 dout<11> dout<10> dout<9> dout<8> dout<7>/mpu<7> dout<6>/mpu<6> drvdd drvss dout<5>/mpu<5> dout<4>/mpu<4> dout<3>/mpu<3> dout<2>/mpu<2> dout<1>/mpu<1> dout<0>/mpu<0> oeb cdsclk1 cdsclk2 adcclk offset<7> offset<6> offset<5> offset<4> offset<3> offset<2> offset<1> dvss dvdd csb rdb wrb offset<0> AD9807 pin descriptions pin no. pin name type description 1, 15 avdd p +5 v analog supply. 2, 10, 12, 14 avss p analog ground. 3, 4 capt ao reference decoupling. see figure 22. 5, 6 capb ao reference decoupling. 7 vref ao internal reference output. decouple with 10 m f + 0.1 m f. 8 cml ao internal bias voltage. decouple with 0.1 m f. 9 vinr ai analog input, red. 11 ving ai analog input, green. 13 vinb ai analog input, blue. 16 strtln di strtln. indicates beginning of scan line. 17 cdsclk1 di cds reset clock pulse input. 18 cdsclk2 di cds data clock pulse input. 19 adcclk di a/d sample clock input. 28, 52 dvss p digital ground. 29, 51 dvdd p +5 v digital supply. 20 offset<7> di pixel rate offset coefficient inputs. most significant bit. 21C26 offset<6:1> di pixel rate offset coefficient inputs. 27 offset<0> di pixel rate offset coefficient inputs. least significant bit. 30 csb di chip select. active low. 31 rdb di read strobe. active low. 32 wrb di write strobe. active low. 33 oeb di output enable. active low. 34 dout<0>/mpu<0> dio data output lsb/register input lsb 35C39, 42 dout<1:6>/mpu<1:6> dio data outputs/register inputs. 40 drvss p digital driver ground 41 drvdd p digital driver supply 43 dout<7>/mpu<7> dio data output/register input msb. 44C46 dout<8:10> do data outputs. 47 dout<11> do data output msb. 48, 49, 50 a0, a1, a2 di register select pins. 53 gain<0> di pixel rate gain coefficient input. lsb. 54C63 gain<1:10> di pixel rate gain coefficient inputs. 64 gain<11> di pixel rate gain coefficient input. msb. type: ai = analog input; ao = analog output; di = digital input; do = digital output; dio = digital input/output; p = power. AD9807/ad9805 C6C rev. 0 pin configuration 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 55 54 53 52 51 50 49 59 58 57 56 pin 1 identifier top view (not to scale) gain<9> gain<8> gain<7> nc gain<6> gain<5> gain<4> gain<3> gain<2> gain<1> gain<0> dvss dvdd a2 a1 avdd avss capt capt capb capb vref cml vinr avss ving avss vinb avss avdd strtln a0 dout<9> dout<8> dout<7> dout<6> dout<5>/mpu<7> dout<4>/mpu<6> drvdd drvss dout<3>/mpu<5> dout<2>/mpu<4> dout<1>/mpu<3> dout<0>/mpu<2> mpu<1> mpu<0> oeb cdsclk1 cdsclk2 adcclk offset<7> offset<6> offset<5> offset<4> offset<3> offset<2> offset<1> dvss dvdd csb rdb wrb offset<0> ad9805 nc nc = no connect pin descriptions pin no. pin name type description 1, 15 avdd p +5 v analog supply. 2, 10, 12, 14 avss p analog ground. 3, 4 capt ao reference decoupling. see figure 22. 5, 6 capb ao reference decoupling. 7 vref ao internal reference output. decouple with 10 m f + 0.1 m f. 8 cml ao internal bias voltage. decouple with 0.1 m f. 9 vinr ai analog input, red. 11 ving ai analog input, green. 13 vinb ai analog input, blue. 16 strtln di strtln. indicates beginning of scan line. 17 cdsclk1 di cds reset clock pulse input. 18 cdsclk2 di cds data clock pulse input. 19 adcclk di a/d sample clock input. 28, 52 dvss p digital ground. 29, 51 dvdd p +5 v digital supply. 20 offset<7> di pixel rate offset coefficient inputs. most significant bit. 21C26 offset<6:1> di pixel rate offset coefficient inputs. 27 offset<0> di pixel rate offset coefficient inputs. least significant bit. 30 csb di chip select. active low. 31 rdb di read strobe. active low. 32 wrb di write strobe. active low. 33 oeb di output enable. active low. 34 mpu<0> dio register input-output lsb. 35 mpu<1> dio register input-output. 36 dout<0>/mpu<2> dio data output lsb/register input-output. 37C39, 42 dout<1:4>/mpu<3:6> dio data output/register input-output. 40 drvss p digital driver ground. 41 drvdd p digital driver supply. 43 dout<5>/mpu<7> dio data output/register input-output msb. 44C46 dout<6:8> do data outputs. 47 dout<9> do data output msb. 48, 49, 50 a0, a1, a2 di register select pins. 53, 54 nc no connection. 55 gain<0> di pixel rate gain coefficient input lsb. 56C63 gain<1:8> di pixel rate gain coefficient inputs. 64 gain<9> di pixel rate gain coefficient input msb. type: ai = analog input; ao = analog output; di = digital input; do = digital output; dio = digital input/output; p = power. AD9807/ad9805 C7C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9807/ad9805 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* with respect parameter to min max units avdd avss C0.5 +6.5 volts avss avdd C6.5 +0.5 volts dvdd dvss C0.5 +6.5 volts agnd dvss C0.3 +0.3 volts avdd dvdd C6.5 +6.5 volts clock input dvss C0.5 dvdd + 0.5 volts digital outputs dvss C0.5 avdd + 0.3 volts ain, vref avss C0.3 avdd + 0.3 volts junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide temperature package package model range description option* AD9807js 0 c to +70 c pqfp s-64 ad9805js 0 c to +70 c pqfp s-64 *s = plastic quad flatpack. definitions of specifications integral nonlinearity linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential linearity error (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a finite width. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. unipolar offset error in the unipolar mode, the first transition should occur at a level 1/2 lsb above analog common. unipolar offset is defined as the deviation of the actual from that point. the unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. gain error the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. power supply rejection power supply rejection specifies the maximum full-scale change from the initial value with the supplies at the various limits. aperture delay aperture delay is a timing measurement between the sampling clocks and the cds. it is measured from the falling edge of the cdsclk2 input to when the input signal is held for conversion in cds mode. in non-cds mode, it is the falling edge of cdsclk1. AD9807/ad9805 C8C rev. 0 r0, g0, b0 r1, g1, b1 rn, gn, bn t ad t ad t c1a t c2c1a t cra t s t h t goh t gos t cp2 t c1ad t aclk t aclk t stl1 rgb rgbr gb analog inputs strtln cdsclk1 cdsclk2 adcclk gain AD9807/ad9805 C9C rev. 0 pixel 0 t s t h t goh t gos t c1b t c2c1b t crb cdsclk1 t c1c2b t c1ad pixel 1 pixel n t ad t ad analog inputs strtln cdsclk2 t stl1 t aclk t aclk g2 g1 g0 t cp2 adcclk gain AD9807/ad9805 C10C rev. 0 t pwr t as t ah t css t csh t dd t dh csb a0, a1, a2 rdb mpu<7:0> figure 3. read timing rgbrgbrgb cdsclk1 strtln rn, gn, bn analog inputs r0, g0, b0 r1, g1, b1 b1 r0 g0 b0 r1 g1 adcclk gain AD9807/ad9805 C11C rev. 0 76543210 8x full scale 4x full scale 2x full scale 10-bit gain, 10-bit offset 11-bit gain, 9-bit offset 12-bit gain, 8-bit offset color0 color1 figure 5. AD9807 configuration register format configuration register/ad9805 the configuration register controls three functions: a color pointer, gain and offset pin configurations, and digital gain scaling. figure 6 shows the ad9805 configuration register. bits 0C2 control the digital scaling function. setting a bit makes the corresponding condition true. resetting bits 0C2 disables and bypasses the digital multiplier. bits 3C5 control the gain and offset pin distribution. resetting bits 3C5 disables and bypasses the digital subtracter and sets the gain word width to 10. setting any bit makes the corresponding condition true. if bit 3 is set, the 2 lsbs of the gain word become the 2 msbs of the offset word. if bit 4 is set, the lsb of the gain word becomes msb of the offset word. bits 6 and 7 direct register data written to the mpu<7:0> bus to the appropriate red, green or blue register. 76 54 3210 8x full scale 4x full scale 2x full scale 8-bit gain, 10-bit offset 9-bit gain, 9-bit offset 10-bit gain, 8-bit offset color0 color1 figure 6. ad9805 configuration register format register overview mpu port map table ii shows the mpu port map. the mpu port map is accessed through pins a0, a1 and a2 of the AD9807/ad9805, and provides the decoding scheme for the various registers of the AD9807/ad9805. when writing or reading from any of the registers, the appropriate bits must be applied to a0Ca2. table ii. mpu port map format a2 a1 a0 register 0 0 0 configuration register 0 0 1 configuration register 2 0 1 0 pga gain register 0 1 1 odd offset register 1 0 0 even offset register 1 0 1 input offset register 1 1 0 reserved 1 1 1 bayer mode configuration register/AD9807 the configuration register controls three functions: a color pointer, gain and offset pin configurations, and digital gain scaling. figure 5 shows the AD9807 configuration register. bits 0C2 control the digital scaling function. setting a bit makes the corresponding condition true. resetting bits 0C2 disables and bypasses the digital multiplier. bits 3C5 control the gain and offset pin distribution. resetting bits 3C5 disables and bypasses the digital subtracter and sets the gain word width to 12. setting any bit makes the corresponding condition true. for example, if bit 3 is set, the 2 lsbs of the gain word become the 2 msbs of the offset word. if bit 4 is set, the lsb of the gain word becomes msb of the offset word. bits 6 and 7 direct register data written to the mpu<7:0> bus to the appropriate red, green or blue register. figure 4. block diagram 12-bit/10-bit a/d pga pga pga green red blue cds mux bandgap reference configuration register 2 8-10 mpu port csb rdb wrb a2 a1 a0 vref offset AD9807/ad9805 C12C rev. 0 color pointer both the AD9807 and the ad9805 use bits 6 and 7 in the configuration register to direct data to the corresponding internal registers. table iii shows the mapping of bits 6 and 7 to their corresponding color. table iii. color pointer map bit 7 bit 6 color register 0 0 red 0 1 green 1 0 blue 1 1 reserved configuration register 2 configuration register 2 controls several functions: color/black and white selection, cds enabling, a/d reference control and input clamp mode. figure 7 shows the AD9807 and ad9805 configuration register 2 format. setting bit 0 enables the three internal cds blocks of the AD9807/ad9805. reset- ting bit 0 disables the internal cds blocks, configuring the part for sha operation. setting bit 1 places the AD9807/ad9805 in single-channel (black & white) mode. in this mode, only one of the three input channels is used. the color bits in the configu- ration register at the time of the last write indicate the particular channel used. resetting bit 1 places the ad980 7/ad9805 in color mode and all th ree input channels are enabled. bits 2-4 control the full-scale input span of the a/d. setting bit 2 results in a 4 v p-p input span. setting bit 3 results in a 2 v p-p full-scale input span. setting bit 4 results in a full-scale span set by an external re ference connected to the vref pin of the AD9807/ ad9805 (full sc ale = 2 vref). resetting bits 2, 3 or 4 disables that particular mode. bits 6 and 7 select the desired clamp m ode (see figure 17). table iv shows the truth table for clamp mode functionality. line clamp mode allows control of the input switch (s1) via cdsclk1 only while strtln is reset. pixel clamp mode allows control of the input switch (s1) via cdsclk1 regardless of the state of strtln. no clamp mode disables the input switch (s1) regardless of the selected mode of cds operation. table iv. clamp mode truth table bit 7 bit 6 clamp mode 0 0 line clamp 0 1 pixel clamp 1 0 no clamp 1 1 reserved 76 54 3210 cdsen black & white adc full scale = 4v adc full scale = 2v external reference set to 0 clamp mode select clamp mode select figure 7. AD9807/ad9805 configuration register 2 format input offset registers the input offset registers control the amount of analog offset applied to the analog inputs prior to the pga portion of the AD9807/ad9805; there is one input offset register for each color. figure 8 shows the input offset register format. the offset range may be varied between C80 mv and 20 mv. the data for mat for the input offset registers is straight bi nary coding. an all zeros data word corresponds to C80 mv. an all ones data word corresponds to 20 mv. the offset is variable in 256 steps. the contents of the color pointer in the configuration register at the time an input offset register is written indicates the color for which that offset setting applies. 76 54 3210 analog offset (lsb) analog offset analog offset analog offset analog offset analog offset analog offset analog offset (msb) figure 8. input offset registers format pga gain registers bits 0C3 of the pga gain registers control the amount of gain applied to the analog inputs prior to the a/d conversion portion of the AD9807/ad9805; there is one pga gain register for each cha nnel. figure 9 shows the pga gain register format. the gain range may be varied between 1 and 4. the data format for the pga gain registers is straight binary coding. an all z eros data word corresponds to an analog gain of 1. an all ones data word corresponds to an analog gain of 4. the gain is variable in 16 steps (see figure 16). the contents of the co lor pointer in the configuration register at the time a pga gain register is written indicates the color for which that gain set ting applies. bits 4C7 of the pga gain registers are reserved. 76 54 3210 pga0 pga1 pga2 pga3 reserved reserved reserved reserved figure 9. pga gain registers format odd, even offset registers the odd and even offset registers provide a means of digitally compensating the odd and even offset error (register imbal- ance) typical of multiplexed ccd imagers; there is one odd and one even offset register for each color. figure 10 shows the AD9807/ad9805 odd and even offset register formats. the data f ormat for the odd and even offset registers is twos complement. the offsets may be varied between positive AD9807/ad9805 C13C rev. 0 127 lsbs and negative 128 lsbs. the offset is variable in 1 lsb increments (see table v). the contents of the color pointer in the configuration register at the time an odd or even register is written indicates the color for which that offset setting applies. 76 54 3210 o/e offset (lsb) o/e offset o/e offset o/e offset o/e offset o/e offset o/e offset o/e offset (msb) figure 10. odd and even offset registers format table v. odd/even offset register coding odd/even register contents offset value 0111 1111 +127 lsb .. .. .. 0000 0001 +1 lsb 0000 0000 0 lsb 1111 1111 C1 lsb .. .. .. 1000 0000 C128 lsb data buses gain AD9807/ad9805 C14C rev. 0 3-channel sha operation this mode of the AD9807/ad9805 enables 3-channel simulta- neous sampling; it differs from the cds sampling mode in that the cds functions are replaced with sample-and-hold amplifiers (shas). cdsclk1 becomes the sample-and-hold clock; cdsclk2 is tied to ground. the input is sampled on the falling edge of cdsclk1. the input signals must be either dc coupled and level shifted, or dc restored prior to driving the vinr, ving, and vinb pins of the AD9807/ad9805 (clamp mode must be disabled). the input signal in this mode is ground-referenced. the offsets of the three input channels are modified by the values stored in the input offset registers. the part does not invert the input signals prior to amplification by the pgas; the settings in the corresponding pga gain registers determine the gains of the pgas. these outputs from the pgas are then routed through a high speed multiplexer to a 12-bit a/d converter (10-bit for ad9805) for digitization; the multiplexer cycles between the red, green and then blue channels. after digitization, the data is modified by the amount indicated in the odd and even offset registers. a digital subtracter allows additional pixel rate offset modification of each color based on the values written to the offset data bus. finally, a digital multiplier allows pixel rate gain modification of each color based on the values written to the gain data bus. latency for the red, green and blue channels is 6 adcclk cycles (9 cycles for the gain and offset bus; see figure 13). the strtln signal indicates the first red, green and blue pixels in a scan line and the red channel is always the first pixel digitized. the state of strtln is evaluated on the rising edges of adcclk. when strtln is low, the internal circuitry is reset on the next rising edge of adcclk; the multiplexer is switched to the red channel and the odd/even circuitry is configured to expect even pixels. after strtln goes high, the first set of pixels is assumed to be even. consecu- tive sets of pixels (red, green and blue) are assumed to alternate between odd and even pixel sets. 1-channel operation with cds this mode of the AD9807/ad9805 enables single-channel, or monochrome, sampling. the ccd waveform is ac coupled to either the vinr, ving, and vinb pin of the AD9807/ad9805 where it is biased at an appropriate voltage level using the on- chip clamp; the input may alternatively be dc coupled if it has already been appropriately level shifted. bits 6 and 7 in the configuration register select the desired input. the internal cds takes two s amples of the incoming pixel data: the first sample (cdsclk1) is taken during the reset time while the second sample (cdsclk2) is taken during the video, or data, portion of the input pixel. the offset of the input signal is modified by the value stored in the input offset register. the voltage difference of the reset level and video level is inverted and amplified by the pga; the setting in the corresponding pga gain register determines the gain of the pga. the output from the pga is then routed through a high-speed multiplexer to a 12-bit a/d converter (10-bit for ad9805) for digitization; the multiplexer does not cycle in this mode. after digitization, the data is modified by the amount indicated in the odd and even offset regis ters. a digital subtracter allows additional pixel rate offset modification of the signal based on the values written to the offset data bus. finally, a digital multiplier allows pixel rate gain modification of the signal based on the values written to the gain data bus. latency is 6 adcclk cycles (7 cycles for the gain and offset bus; see figure 14). the state of strtln is evaluated on the rising edges of adcclk. when strtln is low, the internal circuitry is reset on the next rising edge of adcclk; the odd/even circuitry is configured to expect an even pixel. after strtln goes high, the first pixel is assumed to be even. consecutive pixels (red, green or blue) are assumed to alternate be tween odd and even. the blue and green channels are recommended for single channel operation to achieve the maximum sampling rate; if using red, invert adcclk as shown in figure 1d. 1-channel sha operation this mode of the AD9807/ad9805 enables single-channel, or monochrome sampling; it differs from the cds monochrome sampling mode in that the cds function is replaced with a sample-and-hold amplifier (sha). cdsclk1 becomes the sample-and-hold clock; cdsclk2 is tied to ground. the input is sampled on the falling edge of cdsclk1. the input waveform would typically be either dc coupled and level shifted, or dc restored prior to driving either the vinr, ving and vinb pins of the AD9807/ad9805 (clamp mode must be disabled). bits 6 and 7 in the configuration register select the desired input. the input signal in this mode is ground referenced. the input signal is not inverted prior to amplification by the pga; the setting in the corresponding pga gain register determines the gain of the pga. the offset of the input signal is modified by the value stored in the input offset register. this signal is then routed through a high speed multi plexer to a 12-bit a/d converter (10-bit for ad9805) for digitization; the multiplexer does not cycle in this mode. after digitization, the data is modified by the amount indicated in the odd and even offset registers. a digital subtracter allows additional pixel rate offset modification of the signal based on the values written to the offset data bus. finally, a digital multiplier allows pixel rate gain modification of the signal based on the values written to the gain data bus. latency is 6 adcclk cycles (7 cycles for gain and offset; see figure 15). the state of strtln is evaluated on the rising edges of adcclk. when strtln is low, the internal circuitry is reset on the next rising edge of adcclk; the odd/even circuitry is configured to expect an even pixel. after strtln goes high, the first pixel is assumed to be even. consecutive pixels (red, green or blue) are assumed to alternate between odd and even. the blue and green channels are recommended for single channel operation to achieve the maximum sampling rate; if using red, invert adcclk as shown in figure 1f. 2-channel bayer mode operation with cds this mode of the AD9807/ad9805 enables bayer mode. the ccd waveform is ac coupled to both the ving and vinb pins of the AD9807/ad9805 where it is biased at an appropriate voltage level using the on-c hip cla mp; the input may alterna- tively be dc coupled if it has already been appropriately level shifted. the internal cds takes two samples of the incoming pixel data: the first sample (cdsclk1) is taken during the reset time while the second sample (cdsclk2) is taken during the video, or data, portion of the input pixel. the offset of the input signal is modified by the value stored in the input offset register. the voltage difference of the reset level and video level AD9807/ad9805 C15C rev. 0 r (n?) g (n?) b (n?) r (n?) g (n?) b (n?) r (n) pixel n pixel n+1 pixel n+2 r, g, b r, g, b r, g, b rgbrgbrgb rin, gin, bin cdsclk1 cdsclk2 adcclk data<11:0> g (n+1) b (n+1) r (n+2) g (n+2) b (n+2) r (n+3) gain AD9807/ad9805 C16C rev. 0 pixel n pixel n+1 pixel n+2 r, g, b r, g, b r, g, b rgbrgbrgb r (n?) g (n?) b (n?) r (n?) g (n?) b (n?) rin, gin, bin cdsclk1 adcclk data<11:0> r (n) g (n+1) b (n+1) r (n+2) g (n+2) b (n+2) r (n+3) gain AD9807/ad9805 C17C rev. 0 choosing the input coupling capacitors because of the dc offset present at the output of ccds, it is likely that these outputs will require some form of dc restoration to be compatible with the input requirements of the AD9807/ad9805. to simplify input level shifting, a dc blocking capacitor may be used in conjunction with the internal biasing circuits of the AD9807/ad9805 to accomplish the necessary dc restoration. figure 17 shows the equivalent analog input for the vinr, ving and vinb inputs. i bias s1 v bias AD9807/ad9805 c v in cdsclk1 strtln config reg 2<7> config reg 2<6> config reg 2<0> cdsclk2 cds 5k w 4pf 4pf figure 17. equivalent analog inputs (vinr, ving, and vinb) enabling cds functionality and line clamp mode with bits 0, 6 and 7 in configuration register 2 allows switch s1 to turn on when strtln is low and cdsclk1 goes high. this connects a 5 k w biasing resistor to the inputs. this arrangement acts to bias the average level of the input signal at voltage, v bias . the voltage, v bias , changes depending on the selected pga gain set- ting. specifically, for gain settings from 0 to 5, v bias equals 4 v; for gain settings from 10 to 15, v bias equals 3 v. for gain set- tings between 5 and 10, v bias decreases linearly from 4 v to 3 v. the size of the coupling capacitor is dependent on several factors including signal swing, allowable droop, and acquisition time. the following procedure shows how to determine the recommended range of capacitors. calculating c max the maximum capacitor value is largely dependent on the degree of accuracy and how quickly the input signal must be level-shifted into the valid input range of the degree of accuracy. other factors affecting the speed of the capacitor charging or calculating overall gain the overall gain for the AD9807/ad9805 can accommodate a wide range of input voltage spans. the total gain is a composite of analog gain (from the pgas), digital gain (from the digital multiplier) and the input span setting for the a/d (2 v or 4 v). to determine the overall gain setting for the AD9807/ad9805, always multiply the pga gain setting by the digital gain setting. in addition, the 2 v/4 v reference option can effectively provide analog gain for input signals less than 2 v p-p. overall gain = analog gain digital gain for example, with the pga gain equal to 1 (gain setting equals all zeros) and the digital multiplier equal to 1, the minimum gain equals 1. with these settings, input signals can be as large as 2 v or 4 v depending on the reference setting. alternatively, with the pga gain equal to 4 (gain setting equals all ones) and the digital multiplier equal to 8, the maximum gain equals 32. with the a/d reference span set to 2 v, an input signal span as small as 62.5 mv p-p will produce a digital output spanning from all zeros to all ones. for ranges between 62.5 mv and 4 v, see the digital gain and analog gain sections of the data sheet. analog gain the transfer function of the pga is: analog input = 4 1 + 3 15 - x 15 ? ? where x is the decimal representation of the settings in the pga gain register. figure 16 shows the graph of this transfer function on both a linear and logarithmic scale. the transfer function is approximately linear in db. 12 6 0 10 8 4 2 gain ?db 4.0 2.5 1.0 3.5 3.0 2.0 1.5 gain pga gain setting 013 123456789101112 1415 gain gain (db) figure 16. pga transfer function digital gain the digital multiplier section of the AD9807/ad9805 allows the user to apply gain in addition to that afforded by the analog pga. the minimum gain of the digital multiplier is always 1. the user sets the maximum gain of the digital multiplier to be 8, 4, or 2 with bits 0C2 in the configuration register. (the max gain is the same for all three channels.) the digital gain applied to the output from the digital subtracter is calculated using the equation: digital gain = 1 + gain < n :0 > y ? ? ? ? x ? ? where gain < n :0> is the decimal representation of the gain bus data bits, y = 4096 for the AD9807, y = 1024 for the ad9805, and x equals 1, 3 or 7 depending on bits 0C2 in the configuration register. overall transfer function the overall transfer function for the AD9807 can be calculated as follows: adc out = v in inputoffset () pga gain [] 2 v ref 4096 d out = [ adc out + offset register C offset bus ][ digital gain ] AD9807/ad9805 C18C rev. 0 discharging include the amount of time that input switch s1 is turned on, the input impedance of the AD9807/ad9805 and the output impedance of the circuit driving the coupling capacitor. the impedance of the drive circuit, r out , the input impedance of the AD9807/ad9805, r in , and the desired charging time, t acq , are all known quantities. note that t acq may not necessarily occur over a continuous period of time; it may actually be an accumulation of discrete charging periods. this is typical where cdsclk1 is asserted only during the reset levels of the pixels. in this case, the quantity, m t, may be substituted for t acq , where m is the number of periods cdsclk1 is asserted and t is the period of the assertion. given these quantities, the maximum value for the input coupling capacitor is c omputed from the equation: c max @ t acq r in + r out /ln v c v e ? ? ? ? where v c is the required voltage change across the coupling capacitor and v e is the maximum tolerable error voltage. v c is calculated by taking the difference between the ccds reset level and the internal bias level of the AD9807/ad9805. v e is the level of accuracy to which the input capacitor must be charged and is system dependent. usually the allowable droop of the capacitor voltage is taken into account. this is discussed below. for example, if the ccd output can droop up to 1 volt without affecting the accuracy of the cds, then clamping to within about one tenth of the allowable droop (100 mv) should be sufficient in most cases. calculating c min determining c min is a function of the amount of allowable voltage droop. it is important that the signals at the inputs of the AD9807/ad9805 remain within the supply voltage limits so the cdss are able to accurately digitize the difference between the reset level and the video level. assuming the input voltages are initially biased at the correct levels, the input bias current of the AD9807/ad9805 inputs will discharge the input coupling capacitors resulting in voltage droop. after taking into account any droop, the peaks of the input signal must remain within the required voltage limits of AD9807/ad9805 inputs. specifically, c min is a function of the maximum allowable droop, dv, in one scan line, the number of pixels across one scan line, n, the period of one pixel, t, and the input bias current of the AD9807/ad9805, i bias . c min is calculated from the equation: c min = i bias dv ? ? ? ? n t some examples are given below showing the typical range of capacitor values. example 1 a 5000 pixel ccd running at a 2 mhz (t = 500 ns) has a reset level of 4.5 volts and an output voltage of 1.8 volts. the number of optical black pixels available at the start of a line is 18. using the AD9807/ad9805 with an input span of 4 volts and a pga gain of 2 gives a v bias of 3 volts. if the input signal is clamped to 3 volts during the optical black pixels, the required voltage change on the input capacitor, v c , equals (4.5 C 3) or 1.5 volts and the maximum droop allowable during one line, dv, will be (3 C 1.8) or 1.2 volts before the signal droops below 0 volts. with dv = 1.2 volts, a clamp accuracy of 100 mv should be sufficient (v e =100 mv), but this value can be adjusted. the amount of time available to charge up the i nput capacitor, t acq , will equal the period of cdsclk1 (when the clamp switch is closed) times the number of optical black pixels. with a pixel rate of 2 mhz, cdsclk1 would typically be around 100 ns wide, giving t acq =1800 ns or 1.8 m s. the input impedance of the AD9807 is 5k, and the input bias current is 10 na. assume the source impedance driving the AD9807 is low (r out = 0). c max = (1.8 m s /5 k ) (1/ln (1.5/0.1)) = 133 pf c min = (10 na /1.2) 5000 500 ns = 21 pf note that a capacitor larger than 133 pf would still work, it would just take several lines to charge the input capacitor up to the full v c level. another option to lengthen t acq is by clocking the ccd and cdsclk1 while the transport motor moves the scanner carriage. this would extend t acq to several hundred m s or more, meaning that only very fine adjustment would be needed during the limited number of optical black pixels. example 2 a 7926 pixel ccd running at 2 mhz has a reset level of 6 volts, an output voltage of 2.9 volts and 80 optical black pixels. using the AD9807 with an input span of 4 volts and a pga gain of 1.25, v bias = 4 volts. the maximum required voltage change on the capacitor, v c , is 2 volts and the maximum amount of droop dv for one line is 1.1 volts. t acq will be 80 100 ns or 8 m s, and v e = 100 mv should be sufficient. again, r in = 5k, r out = 0, and i bias = 10 na. c max = (8 m s /5 k ) (1/ln (2/0.1)) @ 534 pf c min = (10 na /1.1) (7926) (500 ns ) = 36 pf again, a larger capacitor may be used if several lines are allowed for to initially charge up the cap, or if the ccd and cdsclk1 are clocked during the moving of the scanner carriage. generating 3-channel timing from a 16 3 master clock generating the required signals for cdsclk1, cdsclk2 and adcclk is easily accomplished with a master clock running 16 the desired per channel pixel rate (i.e., 2 msps pixel rate requires 32 mhz master clock). the timing diagram s hown in figure 18 meets all the minimum and maximum timing specifications. note that a 16 master clock using only rising edges was chosen instead of using both edges of an 8 rate clock to ensure immunity to duty cycle variations. master (32mhz) cdsclk1 cdsclk2 adcclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 500ns figure 18. timing scheme using 16 master clock AD9807/ad9805 C19C rev. 0 to calibrate the AD9807/ad9805 for a particular scan, use the following sequence. set digital gain range yes no set pga gain(s) (input offset = 0mv) scan dark line compute pixel offsets set input offset set odd/even offset set gain/offset bus size set external pixel offset vectors scan white line no adjust pga gain(s) ? compute pixel gains set another color ? yes figure 20. calibration power-on initialization and calibration sequence when the AD9807/ad9805 is powered on, the following sequence should be used to initialize the part to a known state. the digital gain and offset buses are disabled until the calibra- tion sequence. the bayer mode register must be written to and set to zero if this mode is not going to be used. write to configuration register set digital gain range to 000 set gain/offset bus size to 000 set color pointer optional readback from registers write to pga gain register set to gain of one (0000) write to input offset register set to 0mv (11001100) write to configuration 2 register set cds or sha operation set 3-channel or 1-channel mode set adc full-scale range set clamp mode write to bayer mode register set mode on or off yes no change pointer set another color ? figure 19. initialization AD9807/ad9805 C20C rev. 0 no bring strtln high the first pixel is green the second pixel is red, alternating grgr... bring strtln low at the end of the line next line grgr again (new frame) ? yes apply at least one adcclk cycle write a "1" to the lsb of the bayer register bring strtln low set pga and input offset for red pixels using the blue registers set pga and input offset for green pixels using the green registers change the pga and input offset of blue registers for blue pixels bring strtln high the first pixel is blue the second pixel is green, alternating bgbg... bring strtln low at the end of the line change gain and offset for red pixels with blue registers figure 21. bayer mode operation grounding and decoupling figure 22 shows the recommended decoupling capacitors and ground connections for the AD9807/ad9805. notice that all of the power and ground connections are common for the analog and digital portions of the chip. this would be the best way to connect the device on a board containing a large number of digital components. by treating the AD9807/ad9805 as an analog component, the on-board digital circuitry is considered quiet digital and the digital supply pins are connected to the clean analog supply and analog ground plane. for this tech- nique to work well, it is important that the digital supply pins be well decoupled to the analog g round plane and that the digital outputs of the AD9807/ad9805 are buffered to minimize the digital drive current. the buffers would be referred to the digital supply and ground. this scheme is preferable to tying the digital portion of the AD9807/ad9805 to a noisy digital ground and power plane, capacitively co upling noise to the analog circuitry within the device. the ad 9807/ad9805 evaluation boards use this grounding method, shown in figures 26 and 27. if a minimum amount of digital circuitry exists on the board, it is possible that the power and ground connections of the AD9807 can be separated; be sure to maintain a single p oint connection between the two ground planes at the AD9807/ad9805. +5 0.1 f 0.1 f 0.1 f 10 f + 0.1 f + 10 f 0.1 f 0.1 f 0.1 f +5 52 +5 0.1 f 0.1 f +5 28 +5 0.1 f dvss dvdd 29 41 40 51 1 AD9807/ad9805 (pins omitted for clarity) avdd avss capt capt capb capb ref cml avss avss avss avdd dvss drvdd drvss 2 3 4 5 6 7 8 10 12 14 15 dvss dvdd figure 22. AD9807/ad9805 C21C rev. 0 cis application unlike many other integrated circuit ccd signal processors, the AD9807/ad9805 can easily be implemented in imaging systems that do not use a ccd. by disabling the input clamp and the cds blocks, any dc coupled signal within the input limits of the part can be digitized. figure 23 shows a typical block diagram of the AD9807 used with a color cis module, in this case dyna image corporations dl100*. the three color output signals are dc coupled into the AD9807. the dyna cis modules output levels are around 70 mv to 500 mv dark to bright, well within the input range of the AD9807. the AD9807 is config- ured for 3-channel sha operation through the mpu registers. timing u sed with the dyna dl100 is shown in figure 24; the cis output levels are sampled on the falling edge of cdsclk1. the digital asic shown can be implemented in a variety of ways: it could include the mpu interface and timing generator, as well as memory for the output data and pixel gain and offset correction vectors. red green blue cis clocks vinr ving vinb strtln, cdsclk1, adcclk offset<7:0> gain<11:0> timing generator digital asic mpu interface pixel offset correction pixel gain correction dout<11:0> mpu<7:0> a2, a1, a0 oeb, wrb rdb, csb cis 12 7 8 12 8 3 output data AD9807 figure 23. cis application diagram (power, ground, and decoupling omitted) cis start pulse cis clock cis output strtln adcclk cdsclk1 figure 24. cis application timing signals evaluation boards the AD9807 and ad9805 evaluation boards are designed to provide an easy interface to a standard pc, simplifying the task of evaluating the performance of the AD9807/ad9805 with an existing imaging system. the system level block diagram shown in figure 25 illustrates the basic evaluation setup for the AD9807 (the ad9805 is the same). the user needs to supply the analog input signals (such as outputs from a ccd), the AD9807/ad9805s clock signals, a power supply and a printer cable to connect the evaluation board to the pcs parallel port. software is included to allow the user to easily a ccomplish three major tasks: first, configure the AD9807/ad9805 in one of several operating modes (1 channel, 3 channel, cds or sha mode, etc.), second, acquire output data from the part and third, down- load pixel gain and offset correction data to the evaluation board and enable pixel rate shading and offset correction. figures 26 and 27 show the signal routing and decoupling for the AD9807 evaluation board. the evaluation boards are designated with the part numbers AD9807-eb and ad9805-eb. *all trademarks are properties of their respective holders. vinr ving vinb clocks gain offset dout mpu i/o mpu control AD9807 red green blue strtln cdsclk1 cdsclk2 adcclk 4 12 8 12 8 7 fifo buffers, latches, and control logic 8 printer cable pc parallel port AD9807 evaluation board +5v volt power supply analog inputs clock inputs figure 25. evaluation system block diagram AD9807/ad9805 C22C rev. 0 avdd avss capt capt capb capb ref cml vinr avss ving avss vinb avss avdd st_lin a0 d(11) d(10) d(9) d(8) d(7) d(6) drvdd drvss d(5) d(4) d(3) d(2) d(1) d(0) oeb cds1 cds2 adclk off(7) off(6) off(5) off(4) off(3) off(2) off(1) off(0) dvss dvdd csb rdb wrb g(11) g(10) g(9) g(8) g(7) g(6) g(5) g(4) g(3) g(2) g(1) g(0) dvss dvdd a2 a1 AD9807 dvdd c13 0.1 AD9807 databus d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 oeb c15 0.1? dvdd a2 a1 gain 12 c7 0.1? c6 10? c12 0.1? avdd c8 0.1? c10 0.1? c4 0.1? avdd tp7 tp6 tp5 c1 0.01? c2 0.01? c3 0.01? jp3 jp2 jp1 r7 50 w b5 r6 50 w b6 r5 50 w b7 tp5 c27 0.1? + c28 10? + tp14 tp13 tp16 tp15 c25 10? c26 0.1? + +5vd c18 10? c21 0.1? + dvdd avss avdd tp9 startline r4 50 w b1 pl pl pl pl startline tp10 r3 50 w b2 pl cds1 tp11 r2 50 w b3 pl cds2 tp12 r1 50 w b4 pl adc adcclk dvdd 8 offset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 c11 0.1? c14 0.1? figure 26. AD9807 evaluation board (digital circuitry omitted) AD9807/ad9805 C23C rev. 0 +c6 +c28 c27 c4 c11 c8 c12 c10 c7 c15 c14 c13 figure 27. suggested capacitor placement for single-side component layout AD9807/ad9805 C24C rev. 0 c2196C12C1/97 printed in u.s.a. 64-terminal pqfp (s-64) 7 0 0.083 (2.10) 0.077 (1.95) seating plane 0.093 (2.35) max 0.041 (1.03) 0.029 (0.73) standoff 0.010 (0.25) 0.009 (0.23) 0.005 (0.13) pin 1 top view (pins down) 33 48 64 1 17 16 32 49 0.031 (0.80) bsc 0.018 (0.45) 0.012 (0.30) 0.555 (14.10) 0.547 (13.90) 0.687 (17.45) 0.667 (16.95) 0.472 (12.0) bsc 0.472 (12.0) bsc 0.555 (14.10) 0.547 (13.90) 0.687 (17.45) 0.667 (16.95) outline dimensions dimensions shown in inches and (mm). |
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